A barrel shifter takes a data and a shift value as input and outputs the data shifted by the shift value. Conventional barrel shifters exist; however, conventional barrel shifters are typically implemented using fully combinatorial logic and perform the shift in a single cycle. Such conventional barrel shifters have several disadvantages.
First, the conventional, single cycle, fully combinatorial barrel shifters use more gates and take up more space on silicon than a smaller barrel shifter that uses less combinatorial logic.
Second, if the digital system in which the barrel shifter resides has multiple clock cycles to perform the shift operation, then the conventional barrel shifter is only being used at a fraction of its capacity if such conventional barrel shifter completes the task of shifting within a single clock cycle.
Given the foregoing, there is a need for a barrel shifter circuit that is space-efficient and that takes advantage of multiple clock cycles in order to perform the required shift operation.